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| Preliminary Technical Data FEATURES Complete RF detector/controller function >50 dB range at 0.9 GHz (-49 dBm to +2 dBm re 50 ) Accurate scaling from 0.1 GHz to 2.5 GHz Temperature-stable linear-in-dB response Log slope of 23.6 mV/dB, intercept at -59.7 dBm at 0.9 GHz True integration function in control loop Low power: 20 mW at 2.7 V, 38 mW at 5 V 50 dB GSM PA Controller AD8311 Its high sensitivity allows control at low signal levels, thus reducing the amount of power that needs to be coupled to the detector. For convenience, the signal is internally ac-coupled. This high-pass coupling, with a corner at approximately 0.016 GHz, determines the lowest operating frequency. Thus, the source may be dc grounded. The AD8311 provides a voltage output, VAPC, that has the voltage range and current drive to directly connect to most handset power amplifiers' gain control pin. VAPC can swing from 250 mV above ground to within 200 mV below the supply voltage. Load currents of up to 6 mA can be supported. The setpoint control input is applied to pin VSET and has an operating range of 0.25 V-1.4 V. The associated circuit determines the slope and intercept of the linear-in-dB measurement system; these are nominally 23.6 mV/dB and -59.7 dBm at 0.9 GHz. Further simplifying the application of the AD8311, the input resistance of the setpoint interface is over 100 M, and the bias current is typically 0.5 A. The AD8311 is available in a 6-lead wafer-level chip scale package, 1.0 mm x 1.5 mm, and consumes 7.6 mA from a 2.7 V to 5.5 V supply. APPLICATIONS Single, dual, and triple band mobile handset (GSM, DCS, EDGE) Transmitter power control PRODUCT DESCRIPTION The AD8311 is a complete low cost subsystem for the precise control of RF power amplifiers operating in the frequency range 0.1 GHz-2.5 GHz and over a typical dynamic range of 50 dB. It is intended for use in cellular handsets and other batteryoperated wireless devices. The log amp technique provides a much wider measurement range and better accuracy than controllers using diode detectors. In particular, its temperature stability is excellent over a specified range of -40C to +85C. FUNCTIONAL BLOCK DIAGRAM Figure 1. Rev. PrA 04/18/2005 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.326.8703 (c) 2005 Analog Devices, Inc. All rights reserved. AD8311 Preliminary Technical Data Specifications Table 1. VS = 2.7 V, Freq = 0.1 GHz, T = 25C, 52.3 termination on RFIN, unless otherwise noted. Parameter SIGNAL INPUT INTERFACE Specified Frequency Range Input Voltage Range Equivalent dBm Range MEASUREMENT MODE f = 0.1 GHz Input Impedance 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity Conditions RFIN (Pin 6) 1 dB Log Conformance, 0.1 GHz VAPC (Pin 2) to VSET (Pin 3) with inversion stage, Sinusoidal Input Signal No termination resistor TA = +25C -40C < TA < +85C 1 dB Error 1 dB Error tbd tbd tbd tbd 2100 || 790 47 46 +2.5 -44.5 23.8 -58.9 tbd tbd tbd tbd 370 || 110 51 50 +3 -48 23.6 -59.7 tbd tbd tbd tbd 180 || 50 43 42 -5 -48 22.7 -60.8 tbd tbd tbd tbd || pF dB dB dBm dBm mV/dB dBm V V dB/C dB/C || pF dB dB dBm dBm mV/dB dBm V V dB/C dB/C || pF dB dB dBm dBm mV/dB dBm V V dB/C dB/C Min 0.1 1.4 -44 Typ Max 2.5 282 +2 Unit GHz mV rms dBm PIN = -10 dBm PIN = -40 dBm PIN = -10 dBm 25C TA +85C -40C TA +25C No termination resistor TA = +25C -40C < TA < +85C 1 dB Error 1 dB Error tbd tbd tbd tbd f = 0.9 GHz Input Impedance 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity PIN = -10 dBm PIN = -40 dBm PIN = -10 dBm 25C TA +85C -40C TA +25C No termination resistor TA = +25C -40C < TA < +85C 1 dB Error 1 dB Error f = 1.9 GHz Input Impedance 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity PIN = -10 dBm PIN = -40 dBm PIN = -10 dBm 25C TA +85C -40C TA +25C Rev. PrA | Page 2 of 12 Preliminary Technical Data Parameter f = 2.5 GHz Input Impedance 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity Conditions No termination resistor TA = +25C -40C < TA < +85C 1 dB Error 1 dB Error Min Typ 160 || 40 42 41 -6 -48 22.5 -60.6 tbd tbd tbd tbd 0.25 2.42 2.54 0.32 0.4 2.6 Max AD8311 Unit || pF dB dB dBm dBm mV/dB dBm V V dB/C dB/C V V V V mA/A nV/Hz MHz ns ns V/s ns V V dB/mV A M V/s 5.5 tbd 12.9 tbd tbd V mA mA s ns OUTPUT INTERFACE Minimum Output Voltage Maximum Output Voltage vs. Temperature General Limit Output Current Drive Output Noise Small Signal Bandwidth Fall Time Rise Time Slew Rate Response Time VSET INTERFACE Nominal Input Range Logarithmic Scale Factor Bias Current Source Input Resistance Slew Rate POWER INTERFACE Supply Voltage Quiescent Current vs. Temperature Power-On Time Power-Off Time PIN = -10 dBm PIN = -40 dBm PIN = -10 dBm 25C TA +85C -40C TA +25C VAPC (Pin 2) VSET 150mV RL 800 85C, VPOS = 3 V, IOUT =6 mA 2.7 V VPOS 5.5 V, RL = VSET = 1.5 V, RFIN = -50 dBm, Source/Sink RF Input = 2 GHz, 0 dBm, fNOISE = 100 kHz, CFLT = 220 pF RFIN = -10 dBm; From CLPF to VOUT Input Level = off to 0 dBm, 90% to 10% Input Level = 0 dBm to off, 10% to 90% 10%-90%, 1.2 V Step (VSET), Open Loop FLTR = Open VSET (Pin 3) RFIN = 0 dBm; measurement mode RFIN = -50 dBm; measurement mode RFIN = -10 dBm; VSET = 1.4V VPOS - 0.1 tbd/tbd 170 tbd 120 270 7 130 tbd tbd tbd tbd 36 tbd 2.7 tbd tbd 7.6 8.2 tbd tbd VPOS (Pin 1) -40C TA +85C Time from VPOS High to VAPC within 1% of Final Value, VSET 200 mV Time from VPOS Low to VAPC within 1% of Final Value, VSET 200 mV Rev. PrA | Page 3 of 12 AD8311 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Preliminary Technical Data Figure 2. Pin Configuration Table 2. Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic VPOS VAPC VSET FLTR COMM RFIN Function Positive Supply Voltage: 2.7 V to 5.5 V Output. Control voltage for gain control element. Setpoint Input. Nominal input range 0.25 V to 1.4 V. Integrator Capacitor. Connect between FLTR and COMM. Device Common (Ground) RF Input Rev. PrA | Page 4 of 12 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS AD8311 Input Amplitude vs. VSET 10 0.1GHz 0 RF INPUT AMPLITUDE - dBm -10 -20 -30 -40 0.9GHz 1.9GHz 2.5GHz AD8311 AD8311 Log Conformance vs. VSET 4 0.1GHz 3 2 ERROR - dB 0.9GHz 1.9GHz 2.5GHz 1 0 -1 -50 -2 -60 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -3 0.2 0.4 0.6 0.8 V SET - V 1 1.2 1.4 1.6 VSET - V Figure 3. Input Amplitude vs. VSET Figure 6. Log Conformance vs. VSET AD8311 Input Am plitude a nd Log Conform a nce vs. V SET a t 0.1GHz 10 Pin_25degC Pin_-40degC Pin_85degC Error_25degC Error_-40degC Error_85degC 4 10 AD8311 Input Amplitude a nd Log Conforma nce vs. V SET a t 1.9GHz Pin_25degC Pin_-40degC Pin_85degC Error_25degC Error_-40degC Error_85degC 4 0 RF INPUT AMPLITUDE - dBm 3 0 3 -10 2 RF INPUT AMPLITUDE - dBm -10 2 ERROR - dB ERROR - dB -20 1 ERROR - dB -20 1 -30 0 -30 0 -40 Error a t +85degC a nd -40de gC ba se d on de viation from slope a nd inte rcept at +25de gC 0.2 0.4 0.6 0.8 V SET - V 1 1.2 1.4 1.6 -1 -40 Error a t +85de gC a nd -40de gC ba se d on de via tion from slope a nd inte rce pt a t +25de gC 0.2 0.4 0.6 0.8 V SET - V 1 1.2 1.4 1.6 -1 -50 -2 -50 -2 -60 -3 -60 -3 Figure 4. Input Amplitude and Log Conformance vs. VSET at 0.1 GHz; -40C, +25C, and +85C AD8311 Input Am plitude a nd Log Conform a nce vs. V SET a t 0.9GHz 10 Pin_25degC 0 RF INPUT AMPLITUDE - dBm Pin_-40degC Pin_85degC Error_25degC -10 Error_-40degC Error_85degC -20 1 ERROR - dB 2 3 4 Figure 7. Input Amplitude and Log Conformance vs. VSET at 1.9 GHz; -40C, +25C, and +85C AD8311 Input Am plitude a nd Log Conform a nce vs. V SET a t 2.5GHz 10 Pin_25degC 0 RF INPUT AMPLITUDE - dBm Pin_-40degC Pin_85degC Error_25degC -10 Error_-40degC Error_85degC 2 3 4 -20 1 -30 0 -30 0 -40 Error a t +85de gC a nd -40de gC ba se d on de via tion from slope a nd inte rce pt a t +25de gC 0.2 0.4 0.6 0.8 V SET - V 1 1.2 1.4 1.6 -1 -40 Error a t +85de gC a nd -40de gC ba se d on de via tion from slope a nd inte rce pt a t +25de gC -1 -50 -2 -60 -3 -50 -2 -60 0.2 0.4 0.6 0.8 V SET - V 1 1.2 1.4 1.6 -3 Figure 5. Input Amplitude and Log Conformance vs. VSET at 0.9 GHz; -40C, +25C, and +85C Figure 8. Input Amplitude and Log Conformance vs. VSET at 2.5 GHz; -40C, +25C, and +85C Rev. PrA | Page 5 of 12 AD8311 AD8311 Distribution of Error over Temperature at 0.1GHz 3 +2 5d eg C - 4 0d eg C +8 5d eg C 3 Preliminary Technical Data AD8311 Distribution of Error over Temperature at 1.9GHz +2 5d egC - 40 deg C +8 5d egC 2 2 1 ERROR - dB 1 0 ERROR - dB -60 -50 -40 -30 -20 -10 0 10 0 -1 -1 -2 -2 -3 -3 - 60 - 50 - 40 - 30 - 20 - 10 0 10 RF INPUT AMPLITUDE - dBm RF INPUT AMPLITUDE - dBm Figure 9. Distribution of Error over Temperature after Ambient Normalization vs. Input Amplitude at 0.1 GHz AD8311 Distribution of Error over Tem perature at 0.9GHz 3 +25degC - 40degC +85degC 2 Figure 12. Distribution of Error over Temperature after Ambient Normalization vs. Input Amplitude at 1.9 GHz AD8311 Distribution of Error ov e r Te m pe rature at 2.5GHz 3 +25degC - 40degC +85degC 2 1 1 ERROR - dB ERROR - dB - 60 - 50 - 40 - 30 - 20 - 10 0 10 0 0 -1 -1 -2 -2 -3 -3 - 60 - 50 - 40 - 30 - 20 - 10 0 10 RF INPUT AMPLITUDE - dBm RF INPUT AM PLIT UDE - dBm Figure 10. Distribution of Error over Temperature after Ambient Normalization vs. Input Amplitude at 0.9 GHz AD8311 Maximum V APC Voltage vs. Supply Voltage by Load Current 3.5 Vapc_0mA 3.3 Vapc_2mA Vapc_4mA Vapc_6mA 3.1 V APC - V Figure 13. Distribution of Error over Temperature after Ambient Normalization vs. Input Amplitude at 2.5 GHz 2.9 2.7 2.5 2.3 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 VPOS - V Figure 11. Maximum VACP Voltage vs. Supply Voltage by Load Current Figure 14. Input Impedance vs. Frequency; No Termination Resistor Rev. PrA | Page 6 of 12 Preliminary Technical Data AD8311 Figure 15. Power-On and -Off Response with VSET Grounded Figure 18. VAPC Response Time, Full-Scale Amplitude Change, Open-Loop Figure 16. Test Setup for Power-On and -Off Response with VSET Grounded Figure 19. Test Setup for VAPC Response Time 10000 NO IS E S P E CT RAL DE NS IT Y - n V /sqrt(Hz ) CFLT=220pF, RF INPUT=2GHz 1000 RFIN_-50dBm RFIN_-40dBm 100 RFIN_-38dBm RFIN_-35dBm RFIN_-30dBm RFIN_-20dBm RFIN_-10dBm RFIN_0dBm 10 100 1000 10000 100000 1000000 10000000 Figure 17. AC Response from VSET to VAPC FREQUENCY - Hz Figure 20. VACP Noise Spectral Density Rev. PrA | Page 7 of 12 AD8311 AD8311 Slope vs. Frequency; -40degC, +25degC, and +85degC -55 Preliminary Technical Data AD8311 Intercept vs. Frequency; -40degC, +25degC, and +85degC 25 Slope_25degC Slope_-40degC Slope_85degC 24 -57 Intercept_25degC Intercept_-40degC Intercept_85degC INTERCEPT- dBm 0.0 0.5 1.0 1.5 2.0 2.5 SLOPE - mV/dB -59 23 -61 22 -63 21 FREQUENCY - GHz -65 0.0 0.5 1.0 1.5 2.0 2.5 FREQUENCY - GHz Figure 21. Slope vs. Frequency; -40C, +25C, and +85C Figure 23. Intercept vs. Frequency; -40C, +25C, and +85C AD8311 Slope vs. Supply Voltage 25 Slope_0.1GHz Slope_0.9GHz Slope_1.9GHz 24 Slope_2.5GHz AD8311 Intercept vs. Supply Voltage -58 Intercept_0.1GHz Intercept_0.9GHz Intercept_1.9GHz -59 Intercept_2.5GHz SLOPE - mV/dB INTERCEPT - dBm 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -60 23 -61 22 -62 21 -63 2.5 3.0 3.5 4.0 V POS - V 4.5 5.0 5.5 VPOS - V Figure 22. Slope vs. Supply Voltage; -40C, +25C, and +85C Figure 24. Intercept vs. Supply Voltage; -40C, +25C, and +85C Rev. PrA | Page 8 of 12 Preliminary Technical Data DEVICE HANDLING The wafer-level chip scale package consists of solder bumps connected to the active side of the die. The part is lead-free with 95.5% tin, 4.0% silver, and 0.5% copper solder bump composition. The WLCSP package can be mounted on printed circuit boards using standard surface-mount assembly techniques; however, caution should be taken to avoid damaging the die. See the AN-617 application note for additional information. WLCSP devices are bumped die, and exposed die can be sensitive to light condition, which can influence specified limits. AD8311 For operation in controller mode, both jumpers, J1 and J2, should be removed. The setpoint voltage is applied to VSET, RFIN is connected to the RF source (PA output or directional coupler), and VAPC is connected to the gain control pin of the PA. When used in controller mode, a capacitor must be installed in C4 for loop stability (R2 must also be installed, 0 by default). For GSM/DCS handset power amplifiers, this capacitor should typically range from 150 pF to 300 pF. A quasi-measurement mode (where the AD8311 delivers an output voltage that is proportional to the log of the input signal) can be implemented, to establish the relationship between VSET and RFIN, by installing the two jumpers, J1 and J2. This mimics an AGC loop. To establish the transfer function of the log amp, the RF input should be swept while the voltage on VSET is measured, that is, the SMA connector labeled VSET now acts as an output. This is the simplest method to validate operation of the evaluation board. When operated in this mode, a large capacitor (0.01 F or greater) must be installed in C4 (filter capacitor) to ensure loop stability. Also, J3 must be installed to power the inverting amplifier. EVALUATION BOARD Figure 25 shows the schematic of the AD8311 WLCSP evaluation board. The layout and silkscreen of the component and circuit sides are shown in Figure 26 to Figure 29. The board is powered by a single supply in the range, 2.7 V to 5.5 V. The power supply is decoupled by a 0.1 F capacitor. A 100 pF capacitor provides additional supply decoupling, but is not necessary for basic operation. Table 3 details the various configuration options of the evaluation board. Figure 25. Evaluation Board Schematic Rev. PrA | Page 9 of 12 AD8311 Preliminary Technical Data Figure 26. Layout of Component Side (WLCSP) Figure 28. Silkscreen of Component Side (WLCSP) Figure 27. Layout of Circuit Side (WLCSP) Figure 29. Silkscreen of Circuit Side (WLCSP) Table 3. Evaluation Board Configuration Options Component VPOS, GND R1 Function Supply and Ground Vector Pins Input Interface: The 52.3 resistor in Position R1 combines with the AD8311's internal input impedance to give a broadband input impedance of around 50 . Note that the AD8311's RF input is internally ac-coupled. Output Interface: R4 and C3 can be used to check the response of VAPC to capacitive and resistive loading. R3/R4 can be used to reduce the slope of VAPC. Power Supply Decoupling: The nominal supply decoupling consists of a 0.1 F capacitor. C2 can be used for additional supply decoupling. Filter Capacitor: The response time of VAPC can be modified by placing a capacitor between FLTR (Pin 4) and ground. The control loop phase margin can be increased by adding a series resistor. Measurement Mode: A quasi-measurement mode can be implemented by installing J1 and J2 (connecting an inverted VAPC to VSET) to yield the nominal relationship between RFIN and VSET. In this mode, a large capacitor (0.01 F or greater) must be installed in C4. J3 must be installed to power the inverting amplifier. Default Condition Not Applicable R1 = 52.3 (Size 0603) R3, R4, C3 C1, C2 C4, R2 R3 = 0 (Size 0603) R4 = C3 = Open (Size 0603) C1 = 0.1 F (Size 0603) C2 = 100 pF (Size 0603) C4 = Open (Size 0603) R2 = 0 (Size 0603) J1, J2 = Installed J3 = Installed J1, J2, J3 Rev. PrA | Page 10 of 12 Preliminary Technical Data OUTLINE DIMENSIONS AD8311 Figure 30. 6-Lead Wafer-level Chip Scale Package Dimensions shown in mm ORDERING GUIDE AD8311 Products AD8311ACBZ-P71 AD8311-EVAL Temperature Package -40C to +85C Package Description 6-Lead Wafer-level Chip Scale Package, 7" Pocket Tape and Reel Evaluation Board Package Outline CB-6 Branding Information Q04 Ordering Quantity tbd 1 Z = Pb-free part. Rev. PrA | Page 11 of 12 AD8311 NOTES Preliminary Technical Data (c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owers. Printed in the U.S.A. PR05545-0-4/05(PrA) Rev. PrA | Page 12 of 12 |
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